The present invention is directed integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method for forming a gate oxide having a nitrogen bearing species (this invention do not specify any method to form a nitrodized gate oxide, only focus on how to monitor this kind of process) and monitoring a concentration of the nitrogen bearing species to form thin gate dielectric layers for MOS device structures for logic devices. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to a variety of devices such as dynamic random access memory devices, static random access memory devices (SRAM), application specific integrated circuit devices (ASIC), microprocessors and microcontrollers, Flash memory devices, and others.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the ability to prevent impurities from diffusing from a gate region of a device through a gate dielectric to an underlying channel region, which limits the reliability of the transistor device.
As merely an example, dopant impurities migrating from the gate region into the channel region negatively influence operation of the transistor device. Boron impurities often used to dope the gate region are small in size and are able to move about from the gate region. Such boron impurities often migrate from the gate structure, including the gate polysilicon layer, through the gate oxide layer into the channel region. Since the boron impurities are charged species, they often influence a threshold voltage of the transistor device. The threshold voltage often shifts. Other limitations include high charge trapping rates, degradation of P-type channel inverse sub-threshold voltage, poor reliability of the transistor device, and the like.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.